1. Background of the Invention
The invention relates generally to stacked microelectronic modules. Specifically, the invention relates to a method for making a device comprised of stacked integrated circuit (IC) package layers comprising embedded discrete electrical components (e.g., thin or thick film, surface mounted resistors, capacitors and the like, or wire-bonded active or passive components), that are connected to an external circuit.
The ability to form very thin, stackable layers, each containing one or a plurality of homogeneous or heterogeneous integrated circuit chips is desirable and allows high density, high speed systems to be assembled for use in military, space, security and other applications.
Examples of such layers and modules, referred to as “neo-layers” or “neo-stacks” are disclosed in U.S. Pat. No. 6,797,537, Method of Making Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers, U.S. Pat. No. 6,784,547, Stackable Layers Containing Encapsulated Integrated Circuit Chips With One or More Overlying Interconnect Layers, U.S. Pat. No. 6,117,704, Stackable Layer Containing Encapsulated Chips, U.S. Pat. No. 6,072,234, Stack of Equal Layer Neo-Chips Containing Encapsulated IC Chips of Different Sizes and U.S. Pat. No. 5,953,588, Stackable Layers Containing Encapsulated IC Chips, all of which are incorporated fully herein by reference and all of which are assigned to Irvine Sensors Corp., the assignee herein.
2. Brief Summary of the Invention
The present invention discloses a device and method comprising one or more neolayers each containing at least one embedded discreet component such as a thin or thick film surface mount technology (SMT) component or wire bonded component.
A process for forming a neo-layer comprising one or more SMT or wire-bonded discrete components is generally as follows. A first dielectric layer is provided upon a sacrificial substrate. A field metallization layer is then provided upon the first dielectric layer. A first photoresist image is provided upon the field metal to define conductive traces for subsequent electroplating/buildup. The conductive trace pattern preferably includes one or more of the traces terminating at or near the peripheral edge of the layer to be stacked. The cross-section of the trace terminating at the peripheral edge will be exposed to define a conductive edge contact point whereby, when the layer is stacked with other layers, the edge contact point can be connected to another point by means of a conductive T-connect structure.
The first photoresist image is removed after electroplating, the field metal etched, resulting in an electrically conductive set of electroplate traces. The electroplate traces are coated with a second dielectric layer and a second photoresist image defined to delineate predefined via patterns in the layer. Vias are etched into the second dielectric layer to expose desired portions of the electroplate traces to form contact pads. Remaining portions of the second photoresist image are then removed.
A third photoresist image is provided to isolate or expose preselected contact pads, the exposed of which will be provided with an under-bump metal to facilitate later SMT component solder attachment. An under-bump metal is applied to the exposed contact pads at this process step to define an under-bump pad.
The third photoresist image is removed, exposing a second set of contact pads for use a wire bond pads.
SMT discrete components are soldered to the under-bump contact pads at desired locations. Wire bonded components are connected at desired wire bond pads, each of said component types disposed upon an insulating dielectric structure formed by the above photoresist/dielectric process steps.
The entire surface comprising the electroplate traces and components is encapsulated in a non-conductive potting material and the substrate removed to define an upper structure surface and a lower structure surface Predetermined portions of the first and second surface of the structure are removed to a provide a final thickness. A fourth photoresist image is provided on the lower structure surface to define one or more vias through the first dielectric layer for testing of the layer and its components.
The fourth photoresist image is removed, the layer diced to final size resulting in a very thin, high density layer comprising one or more embedded discrete components.
In the above manner, neo-layers containing embedded discrete electronic devices can be efficiently manufactured, stacked and interconnected in a reliable, low cost microelectronic module.
While the claimed embedded discrete device layer apparatus and method has or will be described for the sake of grammatical fluidity with functional explanations, it is to be expressly understood that the claims, unless expressly formulated under 35 USC 112, are not to be construed as necessarily limited in any way by the construction of “means” or “steps” limitations, but are to be accorded the full scope of the meaning and equivalents of the definition provided by the claims under the judicial doctrine of equivalents, and in the case where the claims are expressly formulated under 35 USC 112, are to be accorded full statutory equivalents under 35 USC 112.
The invention and its various embodiments can now be better understood by turning to the following detailed description of the preferred embodiments which are presented as illustrated examples of the invention defined in the claims. It is expressly understood that the invention as defined by the claims may be broader than the illustrated embodiments described below.